SR Flip Flop – Truth Table and Switching Diagram

Unlike combinational logic circuits, sequential logic circuits have some form of in-built memory. Hence, they take into account the previous input state as well as the current ones. Sequential circuits are usually two-state devices which have the output as logic level 1 or logic level 0. In this article, we will talk about one of the most basic sequential circuits, the SR Flip Flop.

SR Flip Flop

SR Flip Flop is a simple flip flop which is a one-bit memory bistable device. It has two inputs – one which sets the device (output 1) labeled “S” and one which resets the device (output 0) labeled R. SR stands for Set-Reset. The reset input ensures that the flip flop resets to its original state depending on the set/reset condition of the device.

The term flip flop relates to the operation of the device – you can flip it to the logical Set state or flop it back to the logical Reset state.

NAND Gate SR Flip Flop

A NAND gate SR flip flop is a basic flip flop. If offers feedback from both outputs to its opposing inputs. It is usually used in memory circuits for storing a single data bit. You can make a basic single bit set-reset SR flip flop as shown below. You connect a pair of cross-coupled dual-input NAND gates to form a Low SR NAND gate Latch. This ensures that each output provides feedback to the other NAND gate inputs. Hence, the device has two inputs S (Set) and R (Reset) along with two corresponding outputs Q and Q’.

The SET State

In the circuit above, if R = 0 and S = 1, then the NAND gate Y has at least one inputs at logic ‘0’. Therefore, as per NAND gate principles, the output Q’ is at logic level 1. This output Q is fed back to input A so that both inputs to the NAND gate X are at logic level 1. Hence, its output is 0.

If the input R = 1 and S = 1, then the NAND gate Y has inputs R = 1 and B = 0. The output Q’ still remains at logic level 1 since at least one of the inputs is at logic 0. Hence, the flip flop is Latched or Set with Q’ = 1 and Q = 0.

The Reset State

In this stable state, Q’ = 0 and Q = 1 where R = 1 and S = 0. As per the NAND gate principles, since one of the inputs of X is at logic level 0, Q = 1. Further, since the output Q is fed back to input B, both the inputs to the NAND gate Y are at logic 1. Hence, Q’ = 0.

If you change the logic of S to 1 with R remaining at logic 1, the output Q’ still remains at logic 0. Hence, the flip flop is Latched or Set. We can define the Set-Reset action using the following Truth Table:

Truth Table for the Set-Reset Function

Set1001Set Q’ = 1
 1101No Change
Reset0110Reset Q’ = 0
 1110No Change
Invalid0011Invalid Condition

SR Flip Flop Switching Diagram

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